imm i"16" $s1v2
llsl $lm[0,8,16,24] $aluf $nowrite
lor $aluf $lm[2,10,18,26] $nowrite
llsl $aluf $ls0v $nowrite
lor $aluf $lm[4,12,20,28] $nowrite
llsl $aluf $ls0v $nowrite
lor $aluf $lm[6,14,22,30] $nowrite
lpassa $aluf $lm32v
llsl $ln[0,8,16,24] $ls0v $nowrite
lor $aluf $ln[2,10,18,26] $nowrite
llsl $aluf $ls0v $nowrite
lor $aluf $ln[4,12,20,28] $nowrite
llsl $aluf $ls0v $nowrite
lor $aluf $ln[6,14,22,30] $lr0v
imm s"1" $ls8v
sxor $lm32v $lr[0,2,4,6] $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[2,4,6,0] $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[4,6,0,2] $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[6,0,2,4] $omr1
spassa $ls8v $lr8v/$imr1
lbsl $lr0v $ls0v $lr0v
sxor $lm32v $aluf $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[2,4,6,0] $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[4,6,0,2] $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[6,0,2,4] $omr1
spassa $ls8v $lr8v/$imr1
lbsl $lr0v $ls0v $lr0v
sxor $lm32v $aluf $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[2,4,6,0] $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[4,6,0,2] $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[6,0,2,4] $omr1
spassa $ls8v $lr8v/$imr1
lbsl $lr0v $ls0v $lr0v
sxor $lm32v $aluf $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[2,4,6,0] $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[4,6,0,2] $omr1
spassa $ls8v $lr8v/$imr1
sxor $lm32v $lr[6,0,2,4] $omr1
spassa $ls8v $lr8v/$imr1
imm i"1" $s17v2
nop
land $lr8v $ls16v $ln[38,46,54,62]
llsr $lr8v $ls0v $lr8v
land $aluf $ls16v $ln[36,44,52,60]
llsr $lr8v $ls0v $lr8v
land $aluf $ls16v $ln[34,42,50,58]
llsr $lr8v $ls0v $lr8v
land $aluf $ls16v $ln[32,40,48,56]
nop/2
l1bmrlor $ln32v $lb0
l1bmrlor $ln40v $lb16
l1bmrlor $ln48v $lb32
l1bmrlor $ln56v $lb48
nop/2
l1bmp $llb0 $llr0v $lln32v
l1bmp $llb8 $llr16v $lln48v
l1bmp $llb16 $llr32v $lln64v
l1bmp $llb24 $llr48v $lln80v
l1bmp $llb32 $llr64v $lln96v
l1bmp $llb40 $llr80v $lln112v
l1bmp $llb48 $llr96v $lln128v
l1bmp $llb56 $llr112v $lln144v
nop
nop
lor $lr0v $ln40v $lr[0,2,8,10]
lor $lr16v $ln56v $lr[4,6,12,14]
nop
lpassa $lr0v $nowrite
lor $lr8v $aluf $ln32v
nop
nop
lor $lr32v $ln72v $lr[0,2,8,10]
lor $lr48v $ln88v $lr[4,6,12,14]
nop
lpassa $lr0v $nowrite
lor $lr8v $aluf $ln40v
nop
nop
lor $lr64v $ln104v $lr[0,2,8,10]
lor $lr80v $ln120v $lr[4,6,12,14]
nop
lpassa $lr0v $nowrite
lor $lr8v $aluf $ln48v
nop
nop
lor $lr96v $ln136v $lr[0,2,8,10]
lor $lr112v $ln152v $lr[4,6,12,14]
nop
lpassa $lr0v $nowrite
lor $lr8v $aluf $ln56v
d getd $lm0n0c0b0m0p0 16
d getd $ln0n0c0b0m0p0 16
d getd $ln32n0c0b0m0p0 16
d getd $ls0n0c0b0m0p0 4
d getd $lr0n0c0b0m0p0 64