imm i"32" $t
llsl $lm0v $aluf $lr0v
llsl $lm8v $t $lr8v
llsl $lm16v $t $lr16v
llsl $lm24v $t $lr24v
llsl $ln0v $t $lr32v
llsl $ln8v $t $lr40v
llsl $ln16v $t $lr48v
llsl $ln24v $t $lr56v
ladd $lm[2,6,10,14] $lr[0,4,8,12] $lr0v
ladd $lm[18,22,26,30] $lr[16,20,24,28] $lr8v
ladd $ln[2,6,10,14] $lr[32,36,40,44] $lr16v
ladd $ln[18,22,26,30] $lr[48,52,56,60] $lr24v
imm f"8388608" $t
ior $lr0v $aluf $nowrite
fvadd $aluf -$t $ls0v
ior $lr8v $t $nowrite
fvadd $aluf -$t $ls8v
ior $lr16v $t $nowrite
fvadd $aluf -$t $lr8v
ior $lr24v $t $nowrite
fvadd $aluf -$t $lr16v
imm ui"0xDEADBEEF" $lr0v
imm ui"0xDEADBEEF" $lr24v
fvmul $ls0v $ls0v $t
nop
fvfma $ls0v $lr2v -$mauf $nowrite
fvfma $ls0v $lr4v -$t $nowrite ; iand $mauf $mauf $nowrite
fvfma $ls0v $lr6v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr8v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr10v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr12v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr14v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr16v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr18v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr20v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr22v -$t $nowrite ; iand $aluf $mauf $nowrite
iand $aluf $mauf $lr100v
fvmul $ls8v $ls8v $t
nop
fvfma $ls8v $lr2v -$mauf $nowrite
fvfma $ls8v $lr4v -$t $nowrite ; iand $mauf $mauf $nowrite
fvfma $ls8v $lr6v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr8v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr10v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr12v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr14v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr16v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr18v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr20v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr22v -$t $nowrite ; iand $aluf $mauf $nowrite
iand $aluf $mauf $lr108v
imm i"32" $t
lbsl $lr8v $aluf $lr8v
lbsl $lr16v $t $lr16v
fvmul $ls0v $ls0v $t
nop
fvfma $ls0v $lr2v -$mauf $nowrite
iand $lr100v $mauf $nowrite
fvfma $ls0v $lr4v -$t $nowrite ; iand $aluf $aluf $nowrite
fvfma $ls0v $lr6v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr8v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr10v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr12v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr14v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr16v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr18v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr20v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls0v $lr22v -$t $nowrite ; iand $aluf $mauf $nowrite
iand $aluf $mauf $lr100v
fvmul $ls8v $ls8v $t
nop
fvfma $ls8v $lr2v -$mauf $nowrite
iand $lr108v $mauf $lr108v
fvfma $ls8v $lr4v -$t $nowrite ; iand $aluf $aluf $nowrite
fvfma $ls8v $lr6v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr8v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr10v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr12v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr14v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr16v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr18v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr20v -$t $nowrite ; iand $aluf $mauf $nowrite
fvfma $ls8v $lr22v -$t $nowrite ; iand $aluf $mauf $nowrite
iand $aluf $mauf $lr108v
iand $ls0v $ls0v $omr1
inot $lr100v $lr100v/$imr1
iand $ls8v $ls8v $omr1
inot $lr108v $lr108v/$imr1
nop
l1bmriand $lr100v $lb0
l1bmriand $lr108v $lb16
nop
nop
l1bmp $lb0 $lr0v $ls0v
l1bmp $lb4 $lr8v $ls8v
l1bmp $lb8 $lr16v $ls16v
l1bmp $lb12 $lr24v $ls24v
l1bmp $lb16 $lr32v $ls32v
l1bmp $lb20 $lr40v $ls40v
l1bmp $lb24 $lr48v $ls48v
l1bmp $lb28 $lr56v $ls56v
iand $lr[0,2] $ls[4,6] $ls[0,2] $lr[0,2]
iand $lr[8,10] $ls[12,14] $ls[8,10]/1100 $lr[8,10]/1100
iand $lr[16,18] $ls[20,22] $ls[16,18] $lr[16,18]/1100
iand $lr[24,26] $ls[28,30] $ls[24,26] $lr[24,26]/1100
iand $lr[32,34] $ls[36,38] $ls[32,34] $lr[32,34]/1100
iand $lr[40,42] $ls[44,46] $ls[40,42] $lr[40,42]/1100
iand $lr[48,50] $ls[52,54] $ls[48,50] $lr[48,50]/1100
iand $lr[56,58] $ls[60,62] $ls[56,58] $lr[56,58]/1100
iand $ls0 $lr2 $ln32/1000
iand $ls8 $lr10 $ln34/1000
iand $ls16 $lr18 $ln36/1000
iand $ls24 $lr26 $ln38/1000
iand $ls32 $lr34 $ln40/1000
iand $ls40 $lr42 $ln42/1000
iand $ls48 $lr50 $ln44/1000
iand $ls56 $lr58 $ln46/1000
nop
nop
ilnot $ln32v $ln32v
nop
nop
ilnot $ln40v $ln40v
nop
nop
ipassa $n32v $lr0v
ipassa $n36v $lr8v
ipassa $n40v $lr16v
ipassa $n44v $lr24v
imm i"32" $t
llsr $lr0v $aluf $ln32v
llsr $lr8v $t $ln40v
llsr $lr16v $t $ln48v
llsr $lr24v $t $ln56v