imm f"1" $s101v2
lxor $ln0v $lm0 $omr1
fvpassa $ls100v $lr0/$imr1; lxor $ln8v $lm0 $omr1
fvpassa $ls100v $lr0/$imr1; lxor $ln16v $lm0 $omr1
fvpassa $ls100v $lr0/$imr1; lxor $ln24v $lm0 $omr1
fvpassa $ls100v $lr0/$imr1; lxor $ln0v $lm2 $omr1
fvpassa $ls100v $lr2/$imr1; lxor $ln8v $lm2 $omr1
fvpassa $ls100v $lr2/$imr1; lxor $ln16v $lm2 $omr1
fvpassa $ls100v $lr2/$imr1; lxor $ln24v $lm2 $omr1
fvpassa $ls100v $lr2/$imr1; lxor $ln0v $lm4 $omr1
fvpassa $ls100v $lr4/$imr1; lxor $ln8v $lm4 $omr1
fvpassa $ls100v $lr4/$imr1; lxor $ln16v $lm4 $omr1
fvpassa $ls100v $lr4/$imr1; lxor $ln24v $lm4 $omr1
fvpassa $ls100v $lr4/$imr1; lxor $ln0v $lm6 $omr1
fvpassa $ls100v $lr6/$imr1; lxor $ln8v $lm6 $omr1
fvpassa $ls100v $lr6/$imr1; lxor $ln16v $lm6 $omr1
fvpassa $ls100v $lr6/$imr1; lxor $ln24v $lm6 $omr1
fvpassa $ls100v $lr6/$imr1; lxor $ln0v $lm8 $omr1
fvpassa $ls100v $lr8/$imr1; lxor $ln8v $lm8 $omr1
fvpassa $ls100v $lr8/$imr1; lxor $ln16v $lm8 $omr1
fvpassa $ls100v $lr8/$imr1; lxor $ln24v $lm8 $omr1
fvpassa $ls100v $lr8/$imr1; lxor $ln0v $lm10 $omr1
fvpassa $ls100v $lr10/$imr1; lxor $ln8v $lm10 $omr1
fvpassa $ls100v $lr10/$imr1; lxor $ln16v $lm10 $omr1
fvpassa $ls100v $lr10/$imr1; lxor $ln24v $lm10 $omr1
fvpassa $ls100v $lr10/$imr1; lxor $ln0v $lm12 $omr1
fvpassa $ls100v $lr12/$imr1; lxor $ln8v $lm12 $omr1
fvpassa $ls100v $lr12/$imr1; lxor $ln16v $lm12 $omr1
fvpassa $ls100v $lr12/$imr1; lxor $ln24v $lm12 $omr1
fvpassa $ls100v $lr12/$imr1; lxor $ln0v $lm14 $omr1
fvpassa $ls100v $lr14/$imr1; lxor $ln8v $lm14 $omr1
fvpassa $ls100v $lr14/$imr1; lxor $ln16v $lm14 $omr1
fvpassa $ls100v $lr14/$imr1; lxor $ln24v $lm14 $omr1
fvpassa $ls100v $lr14/$imr1; lxor $ln0v $lm16 $omr1
fvpassa $ls100v $lr16/$imr1; lxor $ln8v $lm16 $omr1
fvpassa $ls100v $lr16/$imr1; lxor $ln16v $lm16 $omr1
fvpassa $ls100v $lr16/$imr1; lxor $ln24v $lm16 $omr1
fvpassa $ls100v $lr16/$imr1; lxor $ln0v $lm18 $omr1
fvpassa $ls100v $lr18/$imr1; lxor $ln8v $lm18 $omr1
fvpassa $ls100v $lr18/$imr1; lxor $ln16v $lm18 $omr1
fvpassa $ls100v $lr18/$imr1; lxor $ln24v $lm18 $omr1
fvpassa $ls100v $lr18/$imr1; lxor $ln0v $lm20 $omr1
fvpassa $ls100v $lr20/$imr1; lxor $ln8v $lm20 $omr1
fvpassa $ls100v $lr20/$imr1; lxor $ln16v $lm20 $omr1
fvpassa $ls100v $lr20/$imr1; lxor $ln24v $lm20 $omr1
fvpassa $ls100v $lr20/$imr1; lxor $ln0v $lm22 $omr1
fvpassa $ls100v $lr22/$imr1; lxor $ln8v $lm22 $omr1
fvpassa $ls100v $lr22/$imr1; lxor $ln16v $lm22 $omr1
fvpassa $ls100v $lr22/$imr1; lxor $ln24v $lm22 $omr1
fvpassa $ls100v $lr22/$imr1; lxor $ln0v $lm24 $omr1
fvpassa $ls100v $lr24/$imr1; lxor $ln8v $lm24 $omr1
fvpassa $ls100v $lr24/$imr1; lxor $ln16v $lm24 $omr1
fvpassa $ls100v $lr24/$imr1; lxor $ln24v $lm24 $omr1
fvpassa $ls100v $lr24/$imr1; lxor $ln0v $lm26 $omr1
fvpassa $ls100v $lr26/$imr1; lxor $ln8v $lm26 $omr1
fvpassa $ls100v $lr26/$imr1; lxor $ln16v $lm26 $omr1
fvpassa $ls100v $lr26/$imr1; lxor $ln24v $lm26 $omr1
fvpassa $ls100v $lr26/$imr1; lxor $ln0v $lm28 $omr1
fvpassa $ls100v $lr28/$imr1; lxor $ln8v $lm28 $omr1
fvpassa $ls100v $lr28/$imr1; lxor $ln16v $lm28 $omr1
fvpassa $ls100v $lr28/$imr1; lxor $ln24v $lm28 $omr1; l1bmrlor $lr0v $lb0
fvpassa $ls100v $lr28/$imr1; lxor $ln0v $lm30 $omr1;
fvpassa $ls100v $lr30/$imr1; lxor $ln8v $lm30 $omr1; l1bmrlor $lr8v $lb0; l1bmm $lbi $ls0v
fvpassa $ls100v $lr30/$imr1; lxor $ln16v $lm30 $omr1;
fvpassa $ls100v $lr30/$imr1; lxor $ln24v $lm30 $omr1; l1bmrlor $lr16v $lb0; l1bmm $lbi $ls8v
fvpassa $ls100v $lr30/$imr1
msl $ls0v $lr32v
lor $ls0v $aluf $lr0v; l1bmrlor $lr24v $lb0; l1bmm $lbi $ls16v
msl $lr32v $ls0v
lor $lr0v $aluf $lr0v; l1bmm $lbi $ls24v
msl $ls0v $nowrite
lor $lr0v $aluf $ln32v
msl $ls8v $lr40v
lor $ls8v $aluf $lr8v
msl $lr40v $ls8v
lor $lr8v $aluf $lr8v
msl $ls8v $nowrite
lor $lr8v $aluf $ln40v
msl $ls16v $lr48v
lor $ls16v $aluf $lr16v
msl $lr48v $ls16v
lor $lr16v $aluf $lr16v
msl $ls16v $nowrite
lor $lr16v $aluf $ln48v
msl $ls24v $lr56v
lor $ls24v $aluf $lr24v
msl $lr56v $ls24v
lor $lr24v $aluf $lr24v
msl $ls24v $nowrite
lor $lr24v $aluf $ln56v