imm f"1." $ls400/1000
lxor $lm0v $ln0 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln0 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln0 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln0 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln2 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln2 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln2 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln2 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln4 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln4 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln4 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln4 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln6 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln6 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln6 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln6 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln8 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln8 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln8 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln8 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln10 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln10 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln10 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln10 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln12 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln12 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln12 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln12 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln14 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln14 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln14 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln14 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln16 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln16 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln16 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln16 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln18 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln18 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln18 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln18 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln20 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln20 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln20 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln20 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln22 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln22 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln22 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln22 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln24 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln24 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln24 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln24 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln26 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln26 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln26 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln26 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln28 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln28 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln28 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln28 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1; lxor $lm0v $ln30 $omr1
dvadd $lr0v $ls400 $lr0v/$imr1; lxor $lm8v $ln30 $omr1
dvadd $lr8v $ls400 $lr8v/$imr1; lxor $lm16v $ln30 $omr1
dvadd $lr16v $ls400 $lr16v/$imr1; lxor $lm24v $ln30 $omr1
dvadd $lr24v $ls400 $lr24v/$imr1;
msl $lr0v $nowrite
msl $aluf $nowrite; dvadd $lr0v $aluf $nowrite
msl $aluf $nowrite; dvadd $mauf $aluf $nowrite
dvadd $mauf $aluf $lr0v; msl $lr8v $nowrite
msl $aluf $nowrite; dvadd $lr8v $aluf $nowrite
msl $aluf $nowrite; dvadd $mauf $aluf $nowrite
dvadd $mauf $aluf $lr8v; msl $lr16v $nowrite
msl $aluf $nowrite; dvadd $lr16v $aluf $nowrite
msl $aluf $nowrite; dvadd $mauf $aluf $nowrite
dvadd $mauf $aluf $lr16v; msl $lr24v $nowrite
msl $aluf $nowrite; dvadd $lr24v $aluf $nowrite
msl $aluf $nowrite; dvadd $mauf $aluf $nowrite
dvadd $mauf $aluf $lr24v; l1bmrlor $lr0v $lbi
l1bmm $lbi $ln32v; l1bmrlor $lr8v $lbi
l1bmm $lbi $ln40v; l1bmrlor $lr16v $lbi
l1bmm $lbi $ln48v; l1bmrlor $lr24v $lbi
l1bmm $lbi $ln56v