Count Up

Submission Date: 2024/9/1 15:07:24

Status: Accepted

Author: alpha_antares

Lines: 41

VSM

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# r0v=[l2bid(3bit), cycle(2bit), peid[5:3], l1bid(3bit), peid[2:0], 1bit](15bit=32768)
# l2bid
imm i"2" $nowrite
ilsl $l2bid $aluf $r0v
# cycle
zero $s8v
iinc/0001 $aluf $nowrite
iinc/0011 $aluf $nowrite
iinc/0111 $aluf $nowrite
iadd $r0v $aluf $r0v
# peid[5:3]
imm i"3" $s0v
ilsl $r0v $aluf $r0v
ilsr $peid $s0v $nowrite
iadd $r0v $aluf $r0v
# l1bid
ilsl $aluf $s0v $nowrite
iadd $l1bid $aluf $r0v
# peid[2:0]
ilsl $aluf $s0v $r0v
imm i"0b0111" $nowrite
iand $peid $aluf $nowrite
iadd $r0v $aluf $r0v
# 1bit
ipackbit $aluf $s8v $nowrite
iinc $aluf $r0v2
iinc $aluf $r1v2
nop
l1bmd $lr0v $lb0
nop/2
l2bmd $lb0 $lc0
l2bmd $lb32 $lc256
l2bmd $lb64 $lc512
l2bmd $lb96 $lc768
l2bmd $lb128 $lc1024
l2bmd $lb160 $lc1280
l2bmd $lb192 $lc1536
l2bmd $lb224 $lc1792
nop
mvp/n2048 $lc0@0.0 $d0@0
mvp/n2048 $lc0@0.1 $d2048@0
mvp/n2048 $lc0@1.0 $d4096@0
mvp/n2048 $lc0@1.1 $d6144@0
mvp/n2048 $lc0@2.0 $d8192@0
mvp/n2048 $lc0@2.1 $d10240@0
mvp/n2048 $lc0@3.0 $d12288@0
mvp/n2048 $lc0@3.1 $d14336@0
 
 
הההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההה
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Standard Output

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ACCEPTED!! score=41 j=33 m=8 bytes=841
 
 
הההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההה
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Standard Error

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------------------- vsm --------------------
# r0v=[l2bid(3bit), cycle(2bit), peid[5:3], l1bid(3bit), peid[2:0], 1bit](15bit=32768)
# l2bid
imm i"2" $nowrite
ilsl $l2bid $aluf $r0v
# cycle
zero $s8v
iinc/0001 $aluf $nowrite
iinc/0011 $aluf $nowrite
iinc/0111 $aluf $nowrite
iadd $r0v $aluf $r0v
# peid[5:3]
imm i"3" $s0v
ilsl $r0v $aluf $r0v
ilsr $peid $s0v $nowrite
iadd $r0v $aluf $r0v
# l1bid
ilsl $aluf $s0v $nowrite
iadd $l1bid $aluf $r0v
# peid[2:0]
ilsl $aluf $s0v $r0v
imm i"0b0111" $nowrite
iand $peid $aluf $nowrite
 
 
הההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההה
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