Count Up

Submission Date: 2024/9/7 2:59:54
Status: Accepted
Author: dnek
Lines: 29

VSM

ipassa $peid $nowrite
imm i"0b11111000" $ls16v;l1bmd $aluf $lb0
iand $peid $aluf $lr0v # peid & 0b11111000 ...lr0
ior $l1bid $aluf $lr64v
isub $peid $lr0v $nowrite;l1bmp $llb0 $lls80v # 80:0,82:4,84:1,86:5,88:2,90:6,92:3,94:7
d getd $lls80n0c0b0m0p0 4
iadd $aluf $aluf $ls72v
ilsr $lr64v $ls84 $nowrite
sbsl $aluf $ls16v $lr8v # ((lr0 | l1bid) >> 1) << 8 ...lr8
iand $l1bid $ls84 $lr16v # l1bid & 0b1 ...lr16
ilsl $l2bid $ls84 $nowrite;l1bmp $lb0 $s97v # 97: 0, 98: 1, 99: 2, 100: 3
ior $aluf $lr16v $nowrite
ilsl $aluf $ls82 $nowrite #$lr24v # (l2bid << 1) | l1bid & 0b1 ...lr24
ior $ls72v $aluf $nowrite
ior $aluf $lr8v $nowrite
iadd $aluf $ls98 $lr32v # (((peid - lr0) << 1) | lr24 | lr8) + (1, 2)
l1bmd $aluf $lb0;imm i"0x2000" $ls32v #8/pe->32
iadd $lr32v $aluf $lr32v
l1bmd $aluf $lb64
l2bmd $lb0 $lc0;iadd $lr32v $ls32v $lr32v
l2bmd $lb32 $lc256;l1bmd $aluf $lb128
l2bmd $lb64 $lc512;iadd $lr32v $ls32v $lr32v
l2bmd $lb96 $lc768;l1bmd $aluf $lb192
l2bmd $lb128 $lc1024
l2bmd $lb160 $lc1280
l2bmd $lb192 $lc1536
l2bmd $lb224 $lc1792
nop
mvd/n2048 $lc0 $p0@0 #64/l2b->512
mvp/n16384 $p0@0 $d0@0 #64->64
# d geth $lb0n0c0b0 16
# d getd $lls0n0c0b0m0p0 4
# d getd $omr1n0c0b0m0p0 1
הההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההה
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Standard Output

ACCEPTED!! score=29 j=27 m=2 bytes=829
הההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההה
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Standard Error

------------------- vsm --------------------
ipassa $peid $nowrite
imm i"0b11111000" $ls16v;l1bmd $aluf $lb0
iand $peid $aluf $lr0v # peid & 0b11111000 ...lr0
ior $l1bid $aluf $lr64v
isub $peid $lr0v $nowrite;l1bmp $llb0 $lls80v # 80:0,82:4,84:1,86:5,88:2,90:6,92:3,94:7
d getd $lls80n0c0b0m0p0 4
iadd $aluf $aluf $ls72v
ilsr $lr64v $ls84 $nowrite
sbsl $aluf $ls16v $lr8v # ((lr0 | l1bid) >> 1) << 8 ...lr8
iand $l1bid $ls84 $lr16v # l1bid & 0b1 ...lr16
ilsl $l2bid $ls84 $nowrite;l1bmp $lb0 $s97v # 97: 0, 98: 1, 99: 2, 100: 3
ior $aluf $lr16v $nowrite
ilsl $aluf $ls82 $nowrite #$lr24v # (l2bid << 1) | l1bid & 0b1 ...lr24
ior $ls72v $aluf $nowrite
ior $aluf $lr8v $nowrite
iadd $aluf $ls98 $lr32v # (((peid - lr0) << 1) | lr24 | lr8) + (1, 2)
l1bmd $aluf $lb0;imm i"0x2000" $ls32v #8/pe->32
iadd $lr32v $aluf $lr32v
l1bmd $aluf $lb64
l2bmd $lb0 $lc0;iadd $lr32v $ls32v $lr32v
l2bmd $lb32 $lc256;l1bmd $aluf $lb128
l2bmd $lb64 $lc512;iadd $lr32v $ls32v $lr32v
l2bmd $lb96 $lc768;l1bmd $aluf $lb192
l2bmd $lb128 $lc1024
 
 
הההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההה
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX