Mod 3

Submission Date: 2024/9/15 0:21:20

Status: Accepted

Author: spica314

Lines: 63

VSM

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imm i"0xf0" $lr160v2
imm i"4" $lr168v2
imm i"0x0f" $lr176v2
imm i"0xfc" $lr184v2
imm i"2" $lr192v2 
imm i"0x03" $lr200v2
imm i"3" $lr208v2
# (($lm0v2 & 0xf0) >> 4) | ($lm0v2 & 0x0f)
iand $lm0v2 $lr160v2 $ls0v2
ilsr $aluf $lr168v2 $ls8v2
iand $lm0v2 $lr176v2 $ls16v2
iadd $ls8v2 $aluf $ls24v2
# (($ls24v2 & 0xfc) >> 2) | ($ls24v2 & 0x03)
iand $aluf $lr184v2 $ls32v2
ilsr $aluf $lr192v2 $ls40v2
iand $ls24v2 $lr200v2 $ls48v2
iadd $ls40v2 $aluf $ls56v2
# (($ls56v2 & 0xfc) >> 2) | ($ls56v2 & 0x03)
iand $aluf $lr184v2 $ls64v2
ilsr $aluf $lr192v2 $ls72v2
iand $ls56v2 $lr200v2 $ls80v2
iadd $ls72v2 $aluf $ln0v2
# >=3, -3
isub $aluf $lr208v2 $omr1 $ls96v2
ipassa $aluf $ln0v2/$imr1
# (($lm0v2 & 0xf0) >> 4) | ($lm0v2 & 0x0f)
iand $lm8v2 $lr160v2 $ls0v2
ilsr $aluf $lr168v2 $ls8v2
iand $lm8v2 $lr176v2 $ls16v2
iadd $ls8v2 $aluf $ls24v2
# (($ls24v2 & 0xfc) >> 2) | ($ls24v2 & 0x03)
iand $aluf $lr184v2 $ls32v2
ilsr $aluf $lr192v2 $ls40v2
iand $ls24v2 $lr200v2 $ls48v2
iadd $ls40v2 $aluf $ls56v2
# (($ls56v2 & 0xfc) >> 2) | ($ls56v2 & 0x03)
iand $aluf $lr184v2 $ls64v2
ilsr $aluf $lr192v2 $ls72v2
iand $ls56v2 $lr200v2 $ls80v2
iadd $ls72v2 $aluf $ln8v2
# >=3, -3
isub $aluf $lr208v2 $omr1 $ls96v2
ipassa $aluf $ln8v2/$imr1
# (($lm0v2 & 0xf0) >> 4) | ($lm0v2 & 0x0f)
iand $lm16v2 $lr160v2 $ls0v2
ilsr $aluf $lr168v2 $ls8v2
iand $lm16v2 $lr176v2 $ls16v2
iadd $ls8v2 $aluf $ls24v2
# (($ls24v2 & 0xfc) >> 2) | ($ls24v2 & 0x03)
iand $aluf $lr184v2 $ls32v2
ilsr $aluf $lr192v2 $ls40v2
iand $ls24v2 $lr200v2 $ls48v2
iadd $ls40v2 $aluf $ls56v2
# (($ls56v2 & 0xfc) >> 2) | ($ls56v2 & 0x03)
iand $aluf $lr184v2 $ls64v2
ilsr $aluf $lr192v2 $ls72v2
iand $ls56v2 $lr200v2 $ls80v2
iadd $ls72v2 $aluf $ln16v2
# >=3, -3
isub $aluf $lr208v2 $omr1 $ls96v2
ipassa $aluf $ln16v2/$imr1
# (($lm0v2 & 0xf0) >> 4) | ($lm0v2 & 0x0f)
iand $lm24v2 $lr160v2 $ls0v2
ilsr $aluf $lr168v2 $ls8v2
iand $lm24v2 $lr176v2 $ls16v2
iadd $ls8v2 $aluf $ls24v2
# (($ls24v2 & 0xfc) >> 2) | ($ls24v2 & 0x03)
iand $aluf $lr184v2 $ls32v2
ilsr $aluf $lr192v2 $ls40v2
iand $ls24v2 $lr200v2 $ls48v2
iadd $ls40v2 $aluf $ls56v2
# (($ls56v2 & 0xfc) >> 2) | ($ls56v2 & 0x03)
iand $aluf $lr184v2 $ls64v2
ilsr $aluf $lr192v2 $ls72v2
iand $ls56v2 $lr200v2 $ls80v2
iadd $ls72v2 $aluf $ln24v2
# >=3, -3
isub $aluf $lr208v2 $omr1 $ls96v2
ipassa $aluf $ln24v2/$imr1
 
 
הההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההה
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Standard Output

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ACCEPTED!! score=63 j=63 m=0 bytes=1725
 
 
הההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההה
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Standard Error

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------------------- vsm --------------------
# ======= In(0): ((16_MAB:1, 4_PE:1, 16:1, 2_W:1))@LM0 / UInt =======
d set $lm0m0p0 1 000000680000007F # values=[104, 127] / UInt @[0],[1]
d set $lm2m0p0 1 00000061000000C7 # values=[97, 199] / UInt @[2],[3]
d set $lm4m0p0 1 0000005F000000F8 # values=[95, 248] / UInt @[4],[5]
d set $lm6m0p0 1 0000002700000007 # values=[39, 7] / UInt @[6],[7]
d set $lm8m0p0 1 0000001200000096 # values=[18, 150] / UInt @[8],[9]
d set $lm10m0p0 1 000000500000003C # values=[80, 60] / UInt @[10],[11]
d set $lm12m0p0 1 0000006700000098 # values=[103, 152] / UInt @[12],[13]
d set $lm14m0p0 1 0000007C000000D9 # values=[124, 217] / UInt @[14],[15]
d set $lm16m0p0 1 0000005B000000CA # values=[91, 202] / UInt @[16],[17]
d set $lm18m0p0 1 000000BC0000009C # values=[188, 156] / UInt @[18],[19]
d set $lm20m0p0 1 0000008300000010 # values=[131, 16] / UInt @[20],[21]
d set $lm22m0p0 1 00000027000000DB # values=[39, 219] / UInt @[22],[23]
d set $lm24m0p0 1 000000DB000000DA # values=[219, 218] / UInt @[24],[25]
d set $lm26m0p0 1 000000EB000000C1 # values=[235, 193] / UInt @[26],[27]
d set $lm28m0p0 1 000000D600000092 # values=[214, 146] / UInt @[28],[29]
d set $lm30m0p0 1 00000011000000AA # values=[17, 170] / UInt @[30],[31]
d set $lm0m0p1 1 0000001F00000005 # values=[31, 5] / UInt @[32],[33]
d set $lm2m0p1 1 000000E000000083 # values=[224, 131] / UInt @[34],[35]
d set $lm4m0p1 1 000000B2000000AC # values=[178, 172] / UInt @[36],[37]
d set $lm6m0p1 1 0000009400000084 # values=[148, 132] / UInt @[38],[39]
d set $lm8m0p1 1 0000004900000070 # values=[73, 112] / UInt @[40],[41]
d set $lm10m0p1 1 000000B1000000C1 # values=[177, 193] / UInt @[42],[43]
d set $lm12m0p1 1 000000350000003E # values=[53, 62] / UInt @[44],[45]
d set $lm14m0p1 1 0000004400000086 # values=[68, 134] / UInt @[46],[47]
 
 
הההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההההה
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